Copyright(C) 1994,1995,1996,1997 Terumasa KODAKA , Takeshi KONO
■Interrupt controller
Target Normal, High-resolution
Chip 8259A equivalent
Explanation o The PC-9800 (excluding PC-98LT-HA, DB-P1) uses two 8259A
equivalent interrupt controllers (PICs). One is used as the master PIC, which
issues interrupt requests directly to the CPU, and the other is used as the
slave PIC, which issues interrupt requests via the master PIC.
o A conceptual diagram of the connection between the master PIC and the slave
PIC is shown below.
Master PIC
+-----------+
| IR0|←---- IR0(INT 08h)
| IR1|←---- IR1(INT 09h)
| IR2|←---- IR2(INT 0Ah)
CPU←| INT IR3|←---- IR3(INT 0Bh)
| IR4|←---- IR4(INT 0Ch)
| IR5|←---- IR5(INT 0Dh)
| IR6|←---- IR6(INT 0Eh)
| IR7|←+
+-----------+ |
+-----------------+
| Slave PIC
| +-----------+
| | IR0|←---- IR8 (INT 10h)
| | IR1|←---- IR9 (INT 11h)
| | IR2|←---- IR10(INT 12h)
+---|INT IR3|←---- IR11(INT 13h)
| IR4|←---- IR12(INT 14h)
| IR5|←---- IR13(INT 15h)
| IR6|←---- IR14(INT 16h)
| IR7|←---- IR15(INT 17h)
+-----------+
u PC-98LT-HA, DB-P1 use the V50's built-in ICU (Interrupt Control Unit) and do
not have a slave PIC. The V50's built-in ICU is compatible with the μPD71059
(8259A). The I/O address is the same as the master PIC of other models.
o NMI (Non Maskable Interrupt) and SMI (System Management Interrupt) of CPUs
equipped with SMM cannot be controlled by the interrupt controller.
o The I/O addresses related to the interrupt controller are as follows.
------------+-------+-----+-------------------------------------------------
I/O address | Width | R/W | contents
------------+-------+-----+-------------------------------------------------
0000h | BYTE | R/W | Interrupt controller (master)
0002h | BYTE | R/W | Interrupt controller (master)
0008h | BYTE | R/W | Interrupt controller (slave)
000Ah | BYTE | R/W | Interrupt controller (slave)
98D2h | BYTE | R/W | Interrupt mode setting (bits 7-0 = IR7-IR0)
98D4h | BYTE | R/W | Interrupt mode setting (bits 7-0 = IR15-IR8)
------------+-------+-----+-------------------------------------------------
Related I/O 0050h
I/O 0052h
I/O FE8Eh■[PC-9801NS/T･NS/R･P･NX/C･NS/A･NL/R,PC-9821Ne]
I/O 6B8Eh■[PC-9821Nf･Np･Ns･Ne2･Nd･Nm･Lt･Ld,PC-9801NL/A]
I/O 0259h,0A59h - 70~73h
INT 08~17h
I/O 0000h
Name Interrupt Controller (Master)
Target All PC-9800 series
Chip Equivalent to 8259A
Function
See table [Initialize Command Word]
Explanation o Used for initializing the interrupt controller, reading the IRR
(Interrupt Request Register) and ISR (In Service Register), sending EOI (End
Of Interrupt), etc. See the data sheet for details.
o On the PC-9800, "non-special EOI" is used for EOI.
EOI can be issued with
mov al,20h
out 0000h,al
Related I/O 0002h
INT 08-0Fh
I/O 0002h
Name Interrupt controller (master)
Target All PC-9800 series
Chip Equivalent to 8259A
Function
[READ/WRITE]
bit 7: IR7 (INT 0Fh)
bit 6: IR6 (INT 0Eh)
bit 5: IR5 (INT 0Dh)
bit 4: IR4 (INT 0Ch)
bit 3: IR3 (INT 0Bh)
bit 2: IR2 (INT 0Ah)
bit 1: IR1 (INT 09h)
bit 0: IR0 (INT 08h)
1 = Disable interrupt
0 = Enable interrupt
Explanation o Reads and writes the IMR register of the interrupt controller (master).
Also used to write commands (ICW2-ICW4) during initialization.
Related I/O 0000h
INT 08～0Fh
I/O 0008h
Name Interrupt controller (slave)
Target Normal, high resolution
Chip Equivalent to 8259A
Function
See table [Initialize command word]
Explanation o Used to initialize the interrupt controller, read the IRR
(Interrupt Request Register) and ISR (In Service Register), send EOI (End Of
Interrupt), etc. See the data sheet for details.
o On the PC-9800, use "non-special EOI" for EOI.
mov al,20h
out 0008h,al
EOI can be issued. After sending an EOI on the slave PIC, when there are no
more interrupts being serviced on the slave PIC, an EOI must also be issued to
the master PIC.
The following process is performed.
cli
mov al,20h ;Send EOI to SLAVE
out 0008h,al
jmp $+2 ;I/O WAIT
mov al,0Bh ;ISR read mode set(slave)
out 0008h,al
jmp $+2 ;I/O WAIT
in al,0008h ;ISR read(slave)
cmp al,00h ;slave pic in-service ?
jne EoiEnd
mov al,20h ;Send EOI to MASTER
out 0000h,al
EoiEnd: sti
Related I/O 000Ah
INT 10-17h
I/O 000Ah
Name Interrupt controller (slave)
Target Normal, high-resolution
Chip 8259A equivalent
Function
[READ/WRITE]
bit 7: IR15(INT 17h)
bit 6: IR14 (INT 16h)
bit 5: IR13 (INT 15h)
bit 4: IR12 (INT 14h)
bit 3: IR11 (INT 13h)
bit 2: IR10 (INT 12h)
bit 1: IR9 (INT 11h)
bit 0: IR8 (INT 10h)
1 = Disable interrupt
0 = Enable interrupt
Explanation o Reads and writes the IMR register of the interrupt controller (slave).
Also used to write commands (ICW2 to ICW4) during initialization.
Related I/O 0008h
INT 10-17h
Table Initialize command word
The interrupt controller is initialized by the BIOS (ITF) at system startup as
follows. Normally, there is no need for a user program to reinitialize the
interrupt controller.
-------------+--------------------------------------------------------------
Command name | Contents
-------------+--------------------------------------------------------------
ICW1 | bit 7-5: A7-A5
| * Set to 000b on PC-9800 (86-series CPU mode)
| bit 4: Always 1
| bit 3: LTIM
| * Set to 0 on PC-9800 (edge trigger mode)
| * The PC-H98 also supports level trigger mode, but the PIC is set to
| edge trigger because processing is done by an external circuit.
| bit 2: ADI
| * Set to 0 on PC-9800 (86-series CPU mode)
| bit 1: SNGL
| * Set to 0 on PC-9800 (except PC-98LT-HA, DB-P1)
| (not single)
| * Set to 1 on PC-98LT-HA, DB-P1 (single)
| bit 0: IC4
| 0 = Do not send ICW4
| 1 = Send ICW4
-------------+--------------------------------------------------------------
ICW2 | bit 7-3: T7-T3
| * Sets the upper 5 bits of the interrupt vector address
| Set to 00001b on PC-9800 master (INT 08-0Fh)
| Set to 00010b on PC-9800 slave (INT 10-17h)
| (For PC-98HA and DB-P1, set 00010b to the V50 built-in ICU)
| bits 2-0: A10-A8
| * Set to 000b for PC-9800 (86-series CPU mode)
-------------+--------------------------------------------------------------
ICW3 | ■Master PIC
| bits 7-0: S7-S0
| * For PC-9800 (excluding PC-98LT-HA and DB-P1) master
| Set to 10000000b (only IR7 has slave input).
| ■Slave PIC
| bit 7-3: Always 0
| bit 2-0: ID2-ID0
| * Set to 111b for PC-9800 slaves (slave ID)
-------------+--------------------------------------------------------------
ICW4 | bit 7-5: Undefined (always 000b)
| bit 4: SFNM
| 1 = Special free-nested mode
| 0 = Not special free-nested mode
| bit 3: BUF
| * Set to 1 for PC-9800 (buffer mode)
| bit 2: M/S
| * Set to 1 for PC-9800 master
| * Set to 0 for PC-9800 slave
| bit 1: AE01
| * Set to 0 for PC-9800 (normal EOI)
| bit 0: μPM
| * Set to 1 for PC-9800 (86-series CPU mode)
-------------+--------------------------------------------------------------
I/O 98D2h,98D4h
Name PIC interrupt mode control
Undocumented
Target PC-H98
Chip
Function
------------+-------+-----+-------------------------------------------------
I/O address | Width | R/W | Contents
------------+-------+-----+-------------------------------------------------
98D2h | BYTE | R/W |Interrupt mode setting (bit 7-0=IR7-IR0)
98D4h | BYTE | R/W |Interrupt mode setting (bit 7-0=IR15-IR8)
------------+-------+-----+-------------------------------------------------
1 = Level trigger
0 = Edge trigger (compatible with previous version)
Explanation o In PC-H98, interrupt signal lines can also be set to level
trigger. This port is used to set whether each interrupt signal line is used
for edge trigger or level trigger.
o This setting is made to the external circuit of the interrupt controller. On
the PC-9800, the interrupt controller is edge-triggered.
In level-trigger mode, a level-sensitive external circuit generates an
edge-triggered signal to send an interrupt to the interrupt controller.
Related